An Exploration of ATPG Methods for Redacted IP and Reconfigurable Hardware

Automated test-pattern generation (ATPG) is an important step of testing flows that is responsible for generating test values that expose faults in post-fabrication hardware. Previous work has introduced numerous ATPG methods that analyze application functionality to minimize the number of required tests. However, this existing work is misaligned with the emerging trend to use reconfigurable hardware, such as eFPGAs, to redact security-critical IP. When using reconfigurable hardware, application functionality is only known after serially loading a bitstream into a set of configuration flip-flops, which requires ATPG to do more general tests of the reconfigurable hardware as opposed to the targeted application. This more general testing results in prohibitively slow testing times that are on average 14.6× longer than the original design. In this paper, we explore novel ATPG and test methods for reconfigurable hardware to maximize stuck-at fault coverage, while minimizing testing time. We show significantly improved testing times that are on average 1.9× slower than the unredacted designs, without requiring any knowledge of the original application.