Liquid Cooling Of A Stacked Quad-Core Processor And Dram Using Laminar Flow In Microchannels

Three dimensional (3D) stacking of the processor and memory components in high computing applications reduces the communication delay in multicore system-on-a-chip (SoCs) owing to reduced system size and shorter interconnects. The shorter interconnection length between the processing and memory components in a multicore system lowers the overall system access latencies and boosts the system performance. However, this 3D integration of the processors and memory exacerbates the reliability and thermal problems due to high thermal resistance of the stacked designs. Liquid cooling is the most promising solution to overcome this thermal problem arising in the 3D multicore systems. In this paper, we provide a 3D simulation model comprising of quad-core processor, dynamic random-access-memory (DRAM), liquid cooled microchannel heat sink and air-cooled heat sink. The thermal resistance offered by the silicon oxide layer and thermal interface material (TIM) has also been taken into account. The model assumes the integration of the thermal as well as electrical vias and considers the modified thermal conductivity of the materials in the stack. The cores of the quad-core processor are identical, have non-uniform power dissipation and are arranged in a symmetric layout. The quad-core layouts are based on the traditional and optimized floor plan of a single-core microprocessor. The paper reports the results for both planar flow and impingement flow in the microchannels. The thermal efficiency of the 3D design is evaluated on the basis of the hot spot temperature, hot spot spread and number of hot spots on the surface of the chip as well as DRAM.