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My research lies on the boundary between computer architecture and formal methods, and focuses on developing automated formal methodologies and tools for the design and verification of computing systems. My work spans the hardware/software stack, from high-level programming languages down to low-level Verilog circuits. During my PhD, my research focused on the verification of memory consistency model (MCM) properties in parallel hardware and software. MCMs specify the ordering rules for memory operations used for communication and synchronization in shared-memory parallel programs, so MCM verification is critical to parallel system correctness. My work has found real-world bugs in C++ compilers, an open-source processor implementation in Verilog, and in the widely-used RISC-V instruction set (ISA). My work has also enriched the formal methods community by developing new formal analysis techniques.
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2023 Formal Methods in Computer-Aided Design (FMCAD)pp.268-273, (2023)
IEEE Computer Architecture Lettersno. 1 (2023): 41-44
ACM Transactions on Embedded Computing Systemsno. 5s (2023): 1-24
ASPLOS 2023: Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3pp.513-527, (2023)
Proceedings of the 49th Annual International Symposium on Computer Architecture (2022)
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