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个人简介
Camille Jalier received the B.E. degree in electronics, electrical engineering and automation from the École Normale Supérieure Paris (ENS Paris) Saclay, France, in 2007, and the Ph.D. degree in computer architecture from the CEA Laboratory of Electronics and Information Technologies (CEA-Leti), Grenoble, France, in 2010, and the Laboratoire d’informatique, de robotique et de microélectronique de Montpellier (LIRMM), Montpellier, France.
He is a Senior Chief Architect/Expert and the Lab Director at Huawei Technologies France, Grenoble, where he leads technology roadmap and innovation, as well as the SoC architecture for future generation of chipset for networking Gateway equipment. He has more than 15 years of engineering and technology expertise, and he has led teams to design and deliver several generations of multicore and manycore chipset for innovative markets, including autonomous driving, edge AI inference, DPU/SmartNIC, and gateway. Before joining Huawei in 2020, he served as a Chief Architect with Kalray, Montbonnot, France, where he led SoC architecture definition and roadmap with close collaboration with customers, business units, and software platform teams. He also served as the Hardware Director at Kalray, where he led the hardware development team responsible for manycore chipset development from architecture to manufacturing and silicon validation.
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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMSno. 1 (2024): 16-29
2023 60th ACM/IEEE Design Automation Conference (DAC)pp.1-6, (2023)
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