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Amit Jha (Senior Member, IEEE) received the B.S. degree from IIT Madras, Chennai, India, in 2004, the M.S. degree from Pennsylvania State University, University Park, State College, PA, USA, in 2007, and the Ph.D. degree from The University of Texas at Dallas, Richardson, TX, USA, in 2016.
From 2016 to 2017, he was with Jazz Semiconductor, Newport Beach, CA, USA, developing IPs for front-end circuits for 5G applications. From 2007 to 2010, he was a Member of Technical Staff with Maxim Integrated Products, San Jose, CA, USA, where he developed compact models for nanoscale CMOS and LDMOS devices. He is currently a Senior RF/Wireless Engineer with Renesas Electronics, San Jose, where he is developing mm-wave/high-speed circuits for 5G and datacom/telecom applications. His research interests include mm-wave circuit design, frequency synthesis, and compact modeling of transistors.
Dr. Jha was a recipient of the Best Poster Award for “VCO Area Reduction in Nano-Scale CMOS Processes” at SRC-TxACE ICSS Circuits Review in 2014. He is also the Chair of the IEEE Santa Clara Valley Circuits and Systems society.
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2015 Symposium on VLSI Circuits (VLSI Circuits)pp.C302-C303, (2015)
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