Ferroelectric Gate Stack Engineering with Tunnel Dielectric Insert for Achieving High MemoryWindow in FEFETs for NAND Applications
2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)(2024)
摘要
We experimentally demonstrate a novel gate stack engineering technique by introducing a Tunnel Dielectric Layer (TDL) between two Ferroelectric (FE) layers, significantly increasing the Memory Window (MW) in FEFETs. An $\gt 2 \mathrm{X}$ improvement, from $2.9 \mathrm{~V}$ in the reference device (without TDL) to $7.5 \mathrm{~V}$ in the $8 / 3 / 8$ configuration with TDL, was achieved within NAND thickness limit of $20 \mathrm{~nm}$ and write voltage $\leq 15 \mathrm{~V}$. Impact of FE and TDL thickness in MW was also explored.
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关键词
FEFET,TDL,NAND,MW
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