Explainable Port Mapping Inference with Sparse Performance Counters for AMD's Zen Architectures
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3(2024)
摘要
Performance models are instrumental for optimizing performance-sensitive
code. When modeling the use of functional units of out-of-order x86-64 CPUs,
data availability varies by the manufacturer: Instruction-to-port mappings for
Intel's processors are available, whereas information for AMD's designs are
lacking. The reason for this disparity is that standard techniques to infer
exact port mappings require hardware performance counters that AMD does not
provide.
In this work, we modify the port mapping inference algorithm of the widely
used uops.info project to not rely on Intel's performance counters. The
modifications are based on a formal port mapping model with a
counter-example-guided algorithm powered by an SMT solver. We investigate in
how far AMD's processors comply with this model and where unexpected
performance characteristics prevent an accurate port mapping. Our results
provide valuable insights for creators of CPU performance models as well as for
software developers who want to achieve peak performance on recent AMD CPUs.
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