A NoC-Based Spatial DNN Inference Accelerator With Memory-Friendly Dataflow
IEEE Design & Test(2023)
摘要
Editor’s notes: This article addresses the challenges of excessive storage overhead and the absence of sparsity-aware design in Network-on-Chip (NoC)-based spatial deep neural network accelerators. The authors present a prototype chip that outperforms existing accelerators in both energy and area efficiency, demonstrated on TSMC 28-nm process technology. —Mahdi Nikdast, Colorado State University, USA —Miquel Moreto, Barcelona Supercomputing Center, Spain —Masoumeh (Azin) Ebrahimi, KTH Royal Institute of Technology, Sweden —Sujay Deb, IIIT Delhi, India
更多查看译文
关键词
Network on Chip (NoC),deep neural network accelerator,scalable architecture,memory-friendly dataflow,activation sparsity
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要