Design and Implementation of a Low Power Time-to-Digital Converter for Pixel Application

In this paper, a structure for time-to-digital converter (TDC) is proposed. In the structure, three measuring stages with different accuracies are used to reach a high dynamic range. Also in the design, a gated ring oscillator is used to reduce power consumption. The oscillator has an eight phase output, and the TDC resolution reaches to one-eighth of its period. In the circuit, when the stop signal arrives and the digital result is specified, the circuit stops the oscillation of the ring oscillator to prevent further power consumption. The proposed time-to-digital converter is implemented in a 65nm technology. Its resolution is 180ps, its average power consumption is 119 mu W, and its area is 644 mu m(2).