Quality-driven Design Methodology for PUFs in FPGAs for Secure IoT

The emergence of Internet of Things (IoT) has placed strong emphasis on security. Physical Unclonable Functions (PUFs) are a promising low-cost security solution for IoT. Since Field-Programmable Gate Arrays (FPGAs) are more trusted than custom Integrated Circuits (ICs) in building secure systems, implementing PUFs in FPGAs is appealing. In this paper, we propose a methodology for improving the quality of delay-based PUFs on FPGAs. With our method, an asymmetric delay-based PUF has been predictably designed for temperature-and aging-independent operation. Furthermore, the resistance to modeling attacks is built into the design.