An Integrated Circuit Partitioning and TDM Assignment Optimization Framework for Multi-FPGA Systems

In multi-FPGA systems, Time-Division Multiplexing (TDM) is a widely used method for transferring multiple signals over a common wire. The circuit performance will be significantly influenced by this inter-Fpga delay. Some inter-Fpga nets are driven by different clocks, in which case they cannot share the same wire. In this paper, to minimize the maximum delay of inter-Fpga nets, we propose a two-step framework. First, a TDM-aware partitioning algorithm is adopted to minimize the maximum cut size between an FPGA-pair. A TDM ratio assignment method is then applied to assign TDM ratio for each inter-Fpga net optimally. Experimental results show that our algorithm can reduce the maximum TDM ratio significantly within reasonable runtime.