Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition

Saranyu Chattopadhyay,Florian Lonsing,Luca Piccolboni,Deepraj Soni,Peng Wei,Xiaofan Zhang,Yuan Zhou,Luca Carloni,Deming Chen,Jason Cong,Ramesh Karri,Zhiru Zhang,Caroline Trippel,Clark Barrett,Subhasish Mitra

2021 Formal Methods in Computer Aided Design (FMCAD)（2021）

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摘要

Hardware accelerators (HAs) are essential building blocks for fast and energy-efficient computing systems. Accelerator Quick Error Detection (A-QED) is a recent formal technique which uses Bounded Model Checking for pre-silicon verification of HAs. A-QED checks an HA for self-consistency, i.e., whether identical inputs within a sequence of operations always produce the same output. Under modest as...

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关键词

Concurrent computing,Design automation,Scalability,Computer bugs,Programming,Model checking,Logic gates

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