Enhanced Embedded Test Compression Technique For Processing Incompressible Test Patterns

Today, complex circuits are used for various safetycritical applications which require zero defects during manufacturing. This policy implies that numerous test patterns have to be executed to achieve the required test coverage. This leads to a high test data volume and, thus, to increased test costs. Embedded test compression techniques are introduced into the circuit in order to mitigate this effect. The major share of the test patterns can be significantly compressed. However, depending on the test application (e.g. low pin count test), parts of the tests are incompressible due to the architecture and will be rejected. This leads to a test coverage decrease which, in turn, jeopardizes the zero defect policy. Therefore, the rejected test patterns are typically transferred in an uncompressed way while bypassing the compression architecture. However, this is extremely costly. This work proposes a novel architecture that seamlessly combines the advantages of an embedded test compression technique with a lightweight codeword-based compression scheme, which is meant to process specifically the rejected test patterns. The proposed architecture mitigates the adverse impact of rejected test patterns on the compression ratio of state-of-the-art techniques. First experiments already show that a significant compression ratio up to 87.48% is achievable.