Use of Embedded FPGA Resources in Implementations of Five Round Three SHA-3 Candidates

In this paper, we present results of the comprehensive study devoted to the optimization of FPGA implementations of SHA-2 and five SHA-3 finalists using embedded FPGA resources, such as Digital Signal Processing (DSP) units and Block Memories. Our methodology involves implementing, characterizing, and comparing all algorithms with a focus on minimizing the amount of reconfigurable logic resources, and achieving a better balance between the use of reconfigurable and embedded resources. All designs are implemented using four FPGA families, representing major low-cost and high-performance families of Xilinx and Altera.