Handling PCM Resistance Drift with Device , Circuit , Architecture , and System Solutions

Phase Change Memory (PCM) is expected to be incorporated in future memory and storage hierarchies. In recent research, several efforts have been undertaken to overcome PCM limitations of write endurance and write energy. In this paper, we explore a lesser known challenge for PCM – Resistance Drift. Studies have shown that the resistance of a PCM cell increases over time, possibly yielding a wrong state upon read. This is expected to be a frequent source of “soft errors” in PCM devices. The problem is especially significant in multi-level cells (MLCs), where the resistance ranges for each state are more closely spaced. The effect of drift can be negated with a refresh operation that re-writes the contents of a line, similar to refreshes in DRAM devices. However, PCM writes are very expensive in terms of energy, delay, and their effect on endurance, thus making frequent writes infeasible. This paper proposes device, circuit, architecture, and system-level techniques to balance the overhead of refresh with error rate. At the device level, write mechanisms that favor write precision are likely more effective at minimizing the overall efficiency of writes. At the architecture level, we introduce a light-read operation and combine it with ECC support to reduce the need for expensive writes. This basic operation can be augmened with circuit, architectural, and system-level techniques to achieve various trade-offs between energy, latency, soft error rates, and hard error rates. We thus lay the framework for a large family of viable soft error management policies that span the entire system stack.