A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator.

Dong-Hyeon Park,Subhankar Pal,Siying Feng,Paul Gao,Jielun Tan,Austin Rovinski,Shaolin Xie,Chun Zhao,Aporva Amarnath,Timothy Wesley,Jonathan Beaumont,Kuan-Yu Chen,Chaitali Chakrabarti,Michael Bedford Taylor,Trevor N. Mudge,David T. Blaauw,Hun-Seok Kim,Ronald G. Dreslinski

IEEE Journal of Solid-State Circuits（2020）

引用 28|浏览258

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摘要

A sparse matrix-matrix multiplication (SpMM) accelerator with 48 heterogeneous cores and a reconfigurable memory hierarchy is fabricated in 40-nm CMOS. The compute fabric consists of dedicated floating-point multiplication units, and general-purpose Arm Cortex-M0 and Cortex-M4 cores. The on-chip memory reconfigures scratchpad or cache, depending on the phase of the algorithm. The memory and comput...

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关键词

Sparse matrices,Sorting,Indexes,Computer architecture,System-on-chip,Bandwidth,Kernel

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