Reconfigurable very high throughput low latency VLSI (FPGA) design architecture of CRC 32.

Faster data transmission speed and longer distances are more susceptible to errors. CRC (Cyclic Redundancy Checksum) is an efficient and simple cryptic algorithm has been in use among the software community since very long time to detect malicious changes in transmitted data. Recently hardware engineers are also interested in using it in their forward error detection scheme with low resource consumption overhead for their ultra high-speed data communication. To tap the full potential of CRC algorithm in hardware level, it must be implemented in a hardware friendly manner with proper user constraints. This paper presents a very high throughput low latency VLSI design architecture of CRC-32 with reconfigurable parameters. The high throughput is achieved by using expandable data bus line. While, low latency is made possible by parallelizing the logic implementation. The way this problem is approached is elegantly explained using detailed diagrams and mathematics, such that the readers find it easy to adapt the architecture to any CRC polynomial type/size. The uniqueness of our design lies in its ability to operate on the same clock cycle in which the code word is presented, with results produced in immediately next clock cycle. The effects of variations in design parameters of CRC VLSI design on performance characteristics is studied. Also, we have further extended the scope of utility of this component by modeling test scenarios where our CRC logic core is encapsulated to suit different interface standards and how its efficiency changes with chosen interface. HighlightsTo tap the full potential of CRC algorithm in hardware level, it must be implemented in a hardware friendly manner with proper user constraints.The purpose of this work was to develop a CRC design architecture that is fully reconfigurable, got very high throughput and has a single clock latency with data pipelining support.The effects of variations in design parameters of CRC VLSI design on performance characteristics is studied.Also, we have further extended the scope of utility of this component by modeling test scenarios where our CRC logic core is encapsulated to suit different interface standards and how its efficiency changes with chosen interface.The mathematical model discussed is for understanding the operational details of the latency optimized CRC-32 design architecture. It generalizes the architecture to expand data bus width in integral power of 2, and multiplexing of lesser width data lanes into larger width data bus lane.