Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking

Yunsup Lee,Brian Zimmer,Andrew Waterman,Alberto Puggelli,Jaehwa Kwak,Ruzica Jevtic,Ben Keller,Stevo Bailey,Milovan Blagojevic,Pi-Feng Chiu,Henry Cook,Rimas Avizienis,Brian C. Richards,Elad Alon,Borivoje Nikolic,Krste Asanovic

2015 IEEE Hot Chips 27 Symposium (HCS)（2015）

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摘要

This article consists of a collection of slides from the authors' conference presentation. The topics discussed included: Motivation/Raven Project Goals; On-Chip Switched Capacitor DC-DC Converters; Raven3 Chip Architecture; Raven3 Implementation; Raven3 Evaluation; and RISC-V Chip Building at UC Berkeley.

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关键词

RISC-V vector processor,adaptive clocking,UC Berkeley,RISC-V Chip building,Raven3 evaluation,Raven3 implementation,Raven3 chip architecture,on-chip switched capacitor DC-DC converters,Raven Project goals,size 28 nm

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