UTPlaceF: A routability-driven FPGA placer with physical and congestion aware packing
IEEE Trans. on CAD of Integrated Circuits and Systems(2016)
摘要
FPGA packing and placement without routability consideration could lead to unroutable results for high-utilization designs. Conventional FPGA packing and placement approaches are shown to have severe difficulties to yield good routability. In this paper, we propose a FPGA packing and placement engine called UTPlaceF that simultaneously optimizes wirelength and routability. A novel physical and congestion aware packing algorithm and several congestion aware detailed placement techniques are proposed. Compared with the top 3 winners of ISPD'16 FPGA placement contest, UTPlaceF can achieve 3.3%, 7.7% and 28.3% better routed wirelength with similar or shorter runtime.
更多查看译文
关键词
UTPlaceF,routability-driven FPGA placer,FPGA packing,routability consideration,placement engine,wirelength,congestion aware packing algorithm,FPGA placement contest
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要