A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI

Brian Zimmer,Yunsup Lee,Alberto Puggelli,Jaehwa Kwak,Ruzica Jevtic,Ben Keller,Stevo Bailey,Milovan Blagojevic,Pi-Feng Chiu,Hanh-Phuc Le,Po-Hung Chen,Nicholas Sutardja,Rimas Avizienis,Andrew Waterman,Brian C. Richards,Philippe Flatresse,Elad Alon,Krste Asanovic,Borivoje Nikolic

Symposium on VLSI Circuits-Digest of Papers（2015）

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摘要

This work demonstrates a RISC-V vector microprocessor implemented in 28nm FDSOI with fully-integrated non-interleaved switched-capacitor DCDC (SC-DCDC) converters and adaptive clocking that generates four on-chip voltages between 0.5V and 1V using only 1.0V core and 1.8V IO voltage inputs. The design pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices.

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关键词

RISC-V vector microprocessor,tightly integrated switched capacitor,FDSOI,fully-integrated noninterleaved switched-capacitor,SC-DC-DC converters,adaptive clocking,on-chip voltages,dynamic voltage scaling,simple packaging,size 28 nm,voltage 0.5 V to 1 V,voltage 1.8 V,Si

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