Synthesis techniques for application-specific processor-based design

The relentless tracking of Moore's law has led to exponentially increasing transistor counts and results in an explosive growth potential in functionality and the amount of computing power available on a single chip. However, the traditional methods for application-specific integrated circuit (ASIC) design are incapable of handling the increasing design complexity and design challenges. System-level design has been identified as the next productivity boost for the semiconductor industry. At the system-level design, the programmable platforms that are rapidly emerging have become an attractive design alterative to ASIC:s. In this dissertation, we focus on application-specific processor-based platform synthesis, where the primary building blocks are processor cores which can be general-purpose microprocessors, DSP cores and application-specific coprocessors. The platform can be adapted for specific applications by customizing the processor cores, memory elements, their communications, and the application mapping solutions. Effectively, we are extending the standard cell-based methodology for ASIC designs to the application-specific processor-based design methodology. In the first part of the thesis, we focus on synthesis techniques for application-specific instruction set processors. We present a complete synthesis flow and concsponding novel algorithms. We also examine the data bandwidth problem and present a quantitative analysis of the performance degradation due to the data bandwidth limitation. An architectural extension and interesting register binding algorithm have been proposed to address the issue. In the second part of the thesis, we investigate techniques for synthesizing application-specific processor networks (ASPNs). First, novel algorithms have been proposed to map task graphs of stream-oriented applications to homogeneous ASPNs so that the throughput and latency can be optimized simultaneously. Next, we study the heterogeneous ASPNs synthesis problem for reconfigurable high-performance computing. Efficient job scheduling and accelerator selection algorithms have been proposed to achieve the optimal system performance.