Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops

Built-in resiliency features enable a microprocessor to detect and correct errors due to fast dynamic voltage droop events as well as other types of dynamic variations. Timing errors in the microprocessor core as well as read (RD) and write (WR) errors in the 8T SRAM based cache can be detected. As a result, guardbands added for these variations are reduced or eliminated, improving performance and reducing power consumption. Measurements on a 45 nm research microprocessor core demonstrate 41% improvement in throughput or 22% reduction in energy at 0.8 V. Measurements on the cache demonstrate reduction of the minimum operating Vcc (VMIN) by 9% thereby resulting in a 7.5% reduction of net operating power.