Fault-tolerant TSV by using scan-chain test TSV

Fu-Wei Chen,Hui-Ling Ting,TingTing Hwang

ASP-DAC（2014）

引用 7|浏览22

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摘要

In order to increase the yield of 3-D IC, fault-tolerance technique to recover failed TSV is essential. In this paper, an architecture of TSV recovery by using scan-chain test TSV is proposed. With the architecture, only a small amount of redundant TSVs is required to be inserted. Extra TSV area that occurs by our method is much less than that of other methods. Moreover, a 3-D IC scan-chain optimization algorithm is proposed taking into consideration the locations of functional TSVs as well as test TSVs, so that the number of total TSVs including test TSV and extra redundant TSV of a 3-D IC design is effectively reduced.

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关键词

optimisation,integrated circuit testing,fault-tolerance technique,three-dimensional integrated circuits,tsv recovery,fault tolerance,3d ic scan-chain optimization algorithm,integrated circuit yield,3d ic yield,scan-chain test tsv,3d ic design,redundant tsv,extra tsv area

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