Efficient minarea retiming of large level-clocked circuits
DATE（1998）
摘要
Delay-constrained area optimization is an important step in synthesis of VLSI circuits. Minimum area (minarea) retiming is a powerful technique to solve this problem. The minarea retiming problem has been formulated as a linear program; in this work we present techniques for reducing the size of this linear program and efficient techniques for generating it. This results in an efficient minarea retiming method for large level-clocked circuits (with tens of thousands of gates).
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关键词
large level-clocked circuit,delay-constrained area optimization,linear program,efficient minarea,efficient technique,minarea retiming problem,important step,minimum area,powerful technique,vlsi circuit,linear programming,very large scale integration,area,retiming,sequential circuits,design automation,design optimization,optimization,vlsi,vlsi circuits
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