Circuit implementation of a 600 MHz superscalar RISC microprocessor

Mark Matson,Dan Bailey,Shane L. Bell,Larry L. Biro,Steve Butler,John Clouser,Jim Farrell,Mike Gowan,Donald Priore,Kathryn Wilcox

ICCD '98: Proceedings of the International Conference on Computer Design（1998）

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摘要

The circuit techniques used to implement a 600 MHz, out-of-order, superscalar RISC Alpha microprocessor are described. Innovative logic and circuit design created a chip that attains 30+ SpecInt95 and 50+ SpecFP95, and supports a secondary cache bandwidth of 6.4 GB/s. Microarchitectural techniques were used to optimize latencies and cycle time, while a variety of static and dynamic design methods balanced critical path delays against power consumption. The chip relies heavily on full custom design and layout to meet speed and area goals. An extensive CAD suite guaranteed the integrity of the design

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关键词

power consumption,30+ specint95,logic and circuit design,microprocessor chips,cad suite,reduced instruction set computing,50+ specfp95,delays,critical path delays,secondary cache bandwidth,cycle time,logic design,microarchitectural techniques,circuit implementation,alpha microprocessor,latencies,600 mhz superscalar risc microprocessor,bandwidth,circuit design,design optimization,design method,out of order,logic circuits,chip,critical path,microarchitecture

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