Global clustering-based performance-driven circuit partitioning.

ABSTRACTIn this paper, we propose a new global clustering based multi-level partitioning algorithm for performance optimization. Our algorithm computes a delay minimal K-way partition first, then gradually reduces the cutsize while keeping the circuit delay by de-clustering and refinement. Our test results on a set of MCNC sequential examples show that we can reduce the delay by 30%, while increasing the cutsize by 28% on average, when compared with hMetis [5]. Our algorithm consistently outperforms state-of-the-art partitioning algorithms [2, 5, 3] on circuit delay with reasonable cost on the cutsize.