Compiler transformations for electronic system level synthesis

With the rapid increase of complexity in System-on-a-Chip (SoC) design, the synthesis community is moving from RTL (register transfer level) synthesis to a higher level of abstraction. Electronic system level (ESL) synthesis is an electronic design methodology that focuses on optimizations at the higher abstraction level (e.g. behavioral-level and system-level synthesis). ESL synthesis systems accept transaction-level modeling (TLM) language like SystemC or pure software programming languages like C/C++, and generate corresponding software/hardware implementations. By unifying the simulation and synthesis data models, ESL synthesis can dramatically boost productivity and reduce time-to-market. Most ESL synthesis systems share a common infrastructure with compilers. In fact, an ESL synthesis system can be viewed as a special compiler whose target platform is a SoC instead of a general-purpose processor. It is not surprising that many source code analysis and transform techniques in compilers are widely used for design optimization in ESL synthesis systems. However, not all compiler techniques are suitable for ESL synthesis because hardware generally have different architectures with processor systems, e.g., memory organization, the amount of parallelism etc. Despite extensive literature on analysis and transformation techniques for ESL synthesis, this field remains challenging to researchers and presents many open problems. The goal of this thesis is to apply existing or propose new code optimization techniques to improve the QoR of designs, and provide a synthesis-friendly data model to ESL synthesis tools. As a complete approach, we explored some open problems mentioned above at all three levels—task level, loop level and instruction level. Specifically, a new communication synthesis approach is proposed at task level which targets sequential communication media for performance optimization; an automatic memory partitioning algorithm is introduced at loop level for design space exploration; a pattern-based behavior synthesis framework is presented at instruction level to utilize the regularity in programs for FPGA resource reduction. Overall, we observed great improvements on solving different problems in ESL synthesis with code transformation techniques.