Gating

Reduction in test power is important to improve battery lifetime in portable electronic devices employing periodic self-test, to increase reliability of testing and to reduce test cost. In scan-based testing, a significant fraction of total test power is dissipated in the combinational block. In this paper, we present a novel circuit technique to virtually eliminate test power dissipation in combinational logic by masking signal transitions at the logic inputs during scan shifting. We implement the masking effect by inserting an extra supply gating transistor in the VDD to GND path for the first level gates at the outputs of the scan flip-flops. The supply gating transistor is turned off in the s can-in mode, essentially gating the supply. Adding an extra transistor in only one logic level renders significant advantages with res pect to area, delay and power overhead compared to existing methods, which use gating logic at the output of scan flip-flops. Moreov er, the proposed gating technique allows reduction in leakage power by input vector control during scan shifting. Simulation results on ISCAS89 benchmarks show average improvement of 62% in area overhead, 101% in power overhead (in normal mode), and 94% in delay overhead, compared to lowest-cost existing method. switching occurs in the combinational gates during the entire scan-in/out period. It is observed that about 78% of total te st energy is dissipated in the combinational block alone (10). Hence, a low-power scan design should address techniques to reduce power dissipation in the combinational block.