Automatic register banking for low-power clock trees
San Jose, CA（2009）
摘要
We present an automatic register placement technique that enables the synthesis of low-power clock trees for low-power ICs. On 7 industrial designs, comparing to (1) a commercial base flow and (2) the power-aware placement technique in, the technique respectively reduced clock-tree power by 19.0% and 14.9%, total power by 15.3% and 5.2% and WNS under on-chip variation (plusmn10%) by 1.8% and 1.5% on average.
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关键词
commercial base flow,automatic register banking,total power,clock-tree power,industrial design,low-power ics,automatic register placement technique,low-power clock tree,on-chip variation,power-aware placement technique,optimization,registers,capacitance,integrated circuit design,switches,routing,algorithm design and analysis,chip,integrated circuits
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