A Hierarchical Cost Tree Mutation Approach to Optimization of Analog Circuits
18TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: POWER AWARE DESIGN OF VLSI SYSTEMS（2005）
摘要
This paper presents a novel method for systematic design of a composite cost function for typical analog circuit sizing optimization problems involving multiple criteria. A non-linear normalization strategy for objective functions has been proposed and has been shown to be better than the traditional linear normalization functions. A Hierarchical Cost Tree Mutation based dynamic weight adjustment algorithm has been developed, which combines the designersý problem specific knowledge with the dynamic solution state in the current iteration to decide the weights in the next iteration. Experiments on a typical Switched Capacitor analog integrator circuit in
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关键词
dynamic solution state,typical analog circuit,next iteration,dynamic weight adjustment algorithm,tree mutation approach,non-linear normalization strategy,analog circuits,current iteration,typical switched capacitor analog,hierarchical cost,traditional linear normalization function,integrator circuit,switched capacitor,objective function,cost function,optimization problem
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