A methodology for accurate performance evaluation in architecture exploration

We present a system that automatically generates a cycle-accurate and bit-true Instruction Level Simulator (ILS) and a hardware im- plementation model given a description of a target processor. An ILS can be used to obtain a cycle count for a given program run- ning on the target architecture, while the cycle length, die size, and power consumption can be obtained from the hardware implemen- tation model. These figuresallow us to accurately and rapidly eval- uate target architectures within an architecture exploration method- ology for system-level synthesis. In an architecture exploration scheme, both the ILS and the hard- ware model must be generated automatically, else a substantial pro- gramming and hardware design effort has to be expended in each design iteration. Our system uses the ISDL machine description lan- guage to support the automatic generation of the ILS and the hard- ware synthesis model, as well as other related tools.