Improving the test quality for scan-based BIST using a general test application scheme

In this paper, we propose a general test application scheme for existing scan-based BIST architectures. The ob- jective is to further improve the test quality without inserting additional logic to the Circuit Under Test (CUT). The pro- posed test scheme divides the entire test process into multiple test sessions. A different number of capture cycles is applied after scanning in a test pattern in each test session to max- imize the fault detection for a distinct subset of faults. We present a procedure to find the optimal number of capture cy- cles following each scan sequence for every fault. Based on this information, the number of test sessions and the number of capture cycles after each scan sequence are determined to maximize the random testability of the CUT. We conduct experiments on ISCAS89 benchmark circuits to demonstrate the effectiveness of our approach.