The Transmogrifier-2: a 1 million gate rapid prototyping system

FPGA(1997)

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摘要
ABSTRACTThis paper describes the Transmogrifier-2, a second generation multi-FPGA system. The largest version of the system will comprise 16 boards that each contain two Altera 10K50 FPGAs, four I-cube interconnect chips, and up to 8 Mbytes of memory. The inter-FPGA routing architecture of the TM-2 uses a novel interconnect structure, a non-uniform partial crossbar, that provides a constant delay between any two FPGAs in the system. The TM-2 architecture is modular and scalable, meaning that various sized systems can be constructed from the same board, while maintaining routability and the constant delay feature. Other features include a system-level programmable clock that allows single-cycle access to off-chip memory, and programmable clock waveforms with resolution to 10ns. The first Transmogrifier-2 boards have been manufactured and are functional. They have recently been used successfully in some simple graphics acceleration applications.
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rapid prototyping system,index terms— architecture,constant delay feature,rapid-prototyping system,system-level programmable clock,million gate,non-uniform partial crossbar,transmogrifier-2 board,constant delay,memory,second-generation multifield programmable gate,rapid prototype,generation multi-fpga system,tm-2 architecture,programmable clock waveform,edge resolution,largest version,scalability.,field programmable gate array fpga,inter-fpga routing architecture,chip,field programmable gate array,indexing terms
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